1. Field of the Invention
The present invention is generally in the field of semiconductor fabrication and packaging. More specifically, the present invention is in the field of integrating passives on-die.
2. Related Art
Conventional means for realizing passive components such as inductors and transformers include both on-die and off-die approaches. Conventional on-die approaches typically involve utilizing interconnect metal and dielectric formed during various die fabrication steps to form the passive component. A transformer can be fabricated on-die, for example, by patterning interconnect metal deposited on a layer of dielectric to form a pair of cross-coupled inductors.
By way of background, the coupling between the two inductors is called mutual inductance. The quality factor (xe2x80x9cQxe2x80x9d) of an inductor is determined by the formula Q=2xcfx80fL/R, where L is the inductance of the inductor, f is the operating frequency of the inductor and R is the resistance of the inductor. A relatively low quality factor signifies a relatively high energy loss. Therefore, by increasing the quality factors of a transformner""s cross-coupled inductors, the energy loss in the transformer can be reduced. Also, increasing the inductance, or decreasing the resistivity of the inductors will decrease the transformer""s energy loss.
However, attempts in the art to realize on-die passives, such as an on-die transformer, encounter various problems such as unwanted capacitance, low self-resonance frequency and low coefficient of coupling of the transformer""s cross-coupled inductors. These problems become even more severe as the operating frequency of the transformer increases. For example, these problems greatly hinder the design of transformers for use in RF applications in the commercially important wireless communication range of 800 to 2400 MHz. Additionally, because on-die interconnect metal is in most cases less than 1.0 micron thick, the thickness of the inductors is limited, resulting in undesirably high resistivity and, consequently, a low quality factor. Furthermore, on-die transformers take up already limited die space that can be used for other circuits, devices, or components.
As stated above, passives such as transformers can also be realized off-die, for example as a discrete component on the substrate or printed circuit board. However, an off-die transformer suffers from various disadvantages. The off-die transformer requires relatively long off-die wires and interconnect lines to connect the transformer terminals to on-die devices. The relatively long off-die wires and interconnect lines result in added and unwanted resistance, capacitance and inductance, which translate to energy loss. Additionally, interconnects for an off-die transformer are subject to long-term damage from vibration, corrosion, chemical contamination, oxidation and other chemical and physical forces, resulting in reduced long-term reliability. Furthermore, placing a transformer off-die requires assembly of at least two components, i.e. the semiconductor die itself and the off-die transformer. The required assembly of two or more components introduces corresponding reliability issues and also results in greater manufacturing cost.
There is thus a need in the art for an approach for realizing passives such as inductors and transformers having high quality factor, low resistivity and high inductance. There is also a need in the art for realizing passives such as inductors and transformers without consuming additional semiconductor die space.
The present invention is directed to method for integrating passives on-die utilizing under bump metal and related structure. According to one embodiment, a first conductor if fabricated. The first conductor can be fabricated, for example, from a layer of interconnect metal comprising either copper or aluminum and being between approximately 1.0 micron to approximately 2.0 microns thick. In one embodiment, the first conductor is fabricated from a layer of under bump metal comprising either copper or aluminum and being between approximately 2.0 microns to approximately 5.0 microns thick. Following, a first isolation layer is formed over the first conductor.
A second conductor having at least one external pad and comprising under bump metal is next fabricated over the first isolation layer. The second conductor can be fabricated substantially directly above the first conductor, for example, resulting in cross-coupling of the first and second conductors so as to form a transformer. In one embodiment, the first isolation layer can comprise at least one via. Thereafter, a second isolation layer having a hole over the external pad of the second conductor is formed over the second conductor. The first and second isolation layers can comprise, for example, either BCB or polyimide and can be between approximately 5.0 microns to approximately 10.0 microns thick. Subsequently, a bump attach site is fabricated at the hole in the second isolation layer over the external pad of the second conductor.
In one embodiment, the invention is a structure fabricated according to the process steps discussed above. As such, the structure comprises a first conductor over which is situated a first isolation layer. A second conductor comprising under bump metal and having at least one external pad is situated over the first isolation layer. In one embodiment, the first isolation layer comprises at least one via through which the second conductor is connected to the first conductor. Additionally, a second isolation layer having at least one hole over the external pad of the second conductor is situated over the second conductor. Furthermore, the structure comprises a bump attach site situated at the hole in the second isolation layer over the external pad of the second conductor.